A Comparative Study of Performance of AES Final Candidates Using FPGAs
نویسندگان
چکیده
In this paper we study and compare the performance of FPGA-based implementations of the ve nal AES candidates (MARS, RC6, Rijndael, Serpent, and Two sh). FPGAs seem to match extremely well with the operations required by the nal candidates. Among the various time-space implementation tradeo s, we focused primarily on time performance. The time performance metrics are throughput and latency. Throughput corresponds to the amount of data processed per time unit while latency is the time required to adapt an algorithm to the input key. Time performance and area requirement results are provided for all the nal AES candidates. To the best of our knowledge, we are not aware of any published extensive results for all the AES nal candidates. Our FPGA implementations show that superior performance can be achieved compared with software implementations. In particular, the latency is reduced by a factor of 20-700 while the throughput speedup is 4-20.
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